Multiplication Or Division By A Fraction Patents (Class 377/48)

Patent number: 10056890Abstract: A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay line includes, in part, a chain of delay elements configured to generate a multitude of delays of the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.Type: GrantFiled: June 24, 2016Date of Patent: August 21, 2018Assignee: Exar CorporationInventor: Omeshwar Lawange

Patent number: 9680478Abstract: A technique includes driving a node of a stage of a ring counter to a predetermined signal state; and clocking the ring counter to cause the signal state to propagate to at least one additional stage of the ring counter to initialize the ring counter with a reset sequence.Type: GrantFiled: September 23, 2011Date of Patent: June 13, 2017Assignee: Silicon Laboratories Inc.Inventors: Tufan Karalar, David Huitse Shen

Patent number: 9673786Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flipflop. The circuit further includes a slave stage of the flipflop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flipflop. The master stage is responsive to the control signal to control the slave stage.Type: GrantFiled: April 12, 2013Date of Patent: June 6, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin SaintLaurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan AbuRahma, Prayag Bhanubhai Patel

Patent number: 9473147Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.Type: GrantFiled: March 3, 2015Date of Patent: October 18, 2016Assignee: MEDIATEK INC.Inventors: WeiHao Chiu, AngSheng Lin, KunYin Wang

Patent number: 9444465Abstract: A low phase noise frequency divider suitable for use in phase locked loops (PLL) and frequency synthesizers, particular in a fractionalN PLL system having an N frequency divider with a main (M) counter and an auxiliary (A) counter. In some user selectable cases, the count value CM for the M counter is fixed and only the count value CA for the A counter is varied. Having a fixed CM value results in lower phase noise in most cases. For cases where it is not possible to vary CM, then CM is allowed to vary in a conventional manner to retain a full range of functionality.Type: GrantFiled: March 23, 2015Date of Patent: September 13, 2016Assignee: Peregrine Semiconductor CorporationInventor: Gary Chunshien Wu

Patent number: 9257990Abstract: A clock dividing device includes an accumulator that accumulates a first accumulated value and a denominator value and stores a second accumulated value, a register that stores a delayed accumulated value obtained by delaying the second accumulated value, a first comparison operation unit that performs a comparative operation on the second accumulated value and a numerator value and stores the second accumulated value as a greater value if the second accumulated value is greater than or equal to the numerator value, a second comparison operation unit that performs a comparative operation on the delayed accumulated value and the numerator value and stores the delayed accumulated value as a delay greater value if the delayed accumulated value is greater than or equal to the numerator value, and a third comparison operation unit that performs a comparative operation on the greater value and the delay greater value and determines the shape of a clock, wherein the shape of the clock is one of a bypass, a rising edType: GrantFiled: November 18, 2014Date of Patent: February 9, 2016Assignee: Samsung Electronics Co., Ltd.Inventor: JinOok Song

Patent number: 9214943Abstract: A fractional frequency divider counts pulses of a digital input clock signal and enables a clock gating module when a preset count is reached. The clock gating module combines the outputs of two clock gating cells that receive, respectively, the input clock signal and an inverted version of the input clock signal. Output pulses are produced on both positive and negative edges of the input clock signal. This permits generation of output clock pulses that can be set to have a spacing and width granularity of half an input clock period, giving the advantages of low jitter and fine duty cycle control.Type: GrantFiled: October 16, 2014Date of Patent: December 15, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Akshat Gupta, Simon J. Gallimore, Deepak Negi, Garima Sharda

Patent number: 9201447Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.Type: GrantFiled: June 21, 2013Date of Patent: December 1, 2015Assignee: Intel Mobile Communications GmbHInventor: Andreas Menkhoff

Patent number: 9166605Abstract: The proposed invention is about an improved method for serialin and serialout transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jittertolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for lowpower applications since a phase shifter in the data path, which is one of the most powerhungry blocks in conventional DPLL designs, is not required.Type: GrantFiled: March 18, 2013Date of Patent: October 20, 2015Assignee: TeraSquare Co., Ltd.Inventors: Hyeon Min Bae, Tae Hun Yoon, Joon Yeong Lee

Patent number: 9118333Abstract: Integrated circuit devices include programmable dividers, such as fractionalN dividers, which can utilize multimodulus dividers (MMD) therein. A multimodulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P<n:0> during an update time interval and may even fully turn off one or more of the div2/3 cells not participating in a dividebyN operation, where N is a positive integer greater than one. The div2/3 cells are configured to include a modulus input terminal and a modulus output terminal and the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.Type: GrantFiled: August 29, 2013Date of Patent: August 25, 2015Assignee: INTEGRATED DEVICE TECHNOLOGY INC.Inventors: Benedykt Mika, Pengfei Hu

Patent number: 9065449Abstract: A divideby1.5 circuit includes a divideby3 circuit that and a frequency doubler circuit. The divideby3 circuit has few logic elements and provides glitchfree operation with a 50 percent duty cycle output. The frequency doubler circuit is based on phaselocked loop circuitry.Type: GrantFiled: October 28, 2013Date of Patent: June 23, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Ali Atesoglu

Patent number: 9059714Abstract: Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an output signal generally includes first and second flipflops; first, second, and third logic circuits, each configured to function equivalently to a logic OR gate; and an internal frequency dividing circuit configured to generate an output waveform having a frequency that is one half that of an input waveform.Type: GrantFiled: October 28, 2013Date of Patent: June 16, 2015Assignee: QUALCOMM IncorporatedInventors: Ali Sajjadi, Babak VakiliAmini

Patent number: 9054639Abstract: A frequency dividing system, which comprises a control circuit, a first multiple input sharing input level triggering device, a first input level triggering group and a second input level triggering group. The first multiple input sharing input level triggering device receives a first frequency dividing signal to generate a feedback signal according to a level of a first clock signal, or receives a second frequency dividing signal to generate the feedback signal according to a level of a second clock signal. The first/second input level triggering group generates the first/second frequency dividing signal to the first multiple input sharing input level triggering device according to the feedback signal if active; and outputs a fixed voltage to the first multiple input sharing input level triggering device if nonactive.Type: GrantFiled: August 27, 2014Date of Patent: June 9, 2015Assignee: MEDIATEK INC.Inventor: ShengChe Tseng

Patent number: 9013213Abstract: A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phaseshifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.Type: GrantFiled: October 1, 2011Date of Patent: April 21, 2015Assignee: Intel CorporationInventors: Kailash Chandrashekar, Stefano Pellerano

Patent number: 9008261Abstract: An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flyingadder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.Type: GrantFiled: January 14, 2013Date of Patent: April 14, 2015Assignee: Liming XiuInventor: Liming Xiu

Patent number: 8901973Abstract: A multiband frequency multiplier configured to generate frequencies and multiplied frequencies in an integrated system. The multiband frequency multiplier includes a multiband multiplier core with a multiplier core differential amplifier configured to receive a multiplier input signal. A switchable load impedance connects to the multiplier core differential amplifier, and includes n multiplier sections. Each multiplier section includes a section impedance and a section switch. The multiplier core differential amplifier generates an output signal having a frequency substantially equal to k times the input frequency in a range of a selected one of n critical frequencies when a selected one of the section switches corresponding to the selected one of the n critical frequencies is triggered.Type: GrantFiled: April 19, 2013Date of Patent: December 2, 2014Assignee: Keysight Technologies, Inc.Inventors: Eric R. Ehlers, Bobby Yubo Wong

Patent number: 8891725Abstract: A frequency divider is disclosed. The frequency divider includes a multimodulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N?1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multimodulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.Type: GrantFiled: April 29, 2013Date of Patent: November 18, 2014Assignee: QUALCOMM IncorporatedInventor: Emmanouil Terrovitis

Patent number: 8884663Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.Type: GrantFiled: February 25, 2013Date of Patent: November 11, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Steven J. Kommrusch, Zihno Jusufovic

Patent number: 8873699Abstract: Some embodiments of the present disclosure relate to a fractional divider for frequency generation. The fractional divider includes a permutation network including a plurality of phase input terminals and a plurality of permuted phase output terminals with a plurality of propagation paths extending therebetween. Multiple propagation paths extend between a phase input terminal and a permuted phase output terminal. A control unit switches an input signal on the phase input terminal through the multiple propagation paths in time to produce a permuted phase signal on the permuted phase output terminal. A phase selection element individually switches the permuted phase output terminals to an output terminal of the fractional divider in time to generate an output signal. The output signal has an output frequency that is a nonunity fraction of an input frequency of the input signal.Type: GrantFiled: November 21, 2012Date of Patent: October 28, 2014Assignee: Intel Mobile Communications GmbHInventor: Stefan Tertinek

Patent number: 8867695Abstract: A prescalar counter may be configured to repeatedly increment once for each cycle of a clock signal at a first frequency and reset upon reaching a threshold counter value. The prescalar counter may also include toggling logic configured to generate a clock pulse of a global time base signal upon each reset of the prescalar counter. A frequency divider may be configured to divide the global time base signal into a plurality of separate clock signals with each of the separate clock signals having a different frequency. The frequency divider may also be configured to provide, to each of a plurality of timers, one of the separate clock signals.Type: GrantFiled: January 25, 2013Date of Patent: October 21, 2014Assignee: Apple Inc.Inventor: Gilbert Herbeck

Patent number: 8867696Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.Type: GrantFiled: June 29, 2011Date of Patent: October 21, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Grenoble 2) SAS, Centre National de la Recherche ScientifiqueInventors: Nicolas Regimbal, Franck Badets, Yann Deval, JeanBaptiste Begueret

Publication number: 20140185736Abstract: A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phaseshifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.Type: ApplicationFiled: October 1, 2011Publication date: July 3, 2014Inventors: Kailash Chandrashekar, Stefano Pellerano

Patent number: 8693616Abstract: An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that generates the control signal to program the shift register.Type: GrantFiled: March 27, 2012Date of Patent: April 8, 2014Assignee: Altera CorporationInventors: Chuan Thim KhoÅ•, Teng Chow Ooi

Patent number: 8675810Abstract: Disclosed is a method and apparatus for a modular high performance low power divider with 50/50 duty cycle output. The modularity offers custom dividers to be quickly developed while maintaining minimum power usage. A multimodulus divider (MMD) receives an input signal and outputs an MMD output signal. The MMD includes a chain of modulus divider stages in such a way as to generate any divide value from 1 to 2(n+1)?1 (n is the number of cascaded elements) while maintaining a 50/50 duty cycle output. Power can be dramatically reduced as the frequency of each subsequent element is halved. The modular nature allows rapid development of any dividers simply by adding more elements to the chain.Type: GrantFiled: June 29, 2012Date of Patent: March 18, 2014Assignee: Intel CorporationInventor: Alan J. Martin

Patent number: 8664933Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a highfrequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the highfrequency component reduced.Type: GrantFiled: May 20, 2010Date of Patent: March 4, 2014Assignee: Seiko Epson CorporationInventor: Masayoshi Todorokihara

Publication number: 20140003569Abstract: Disclosed is a method and apparatus for a modular high performance low power divider with 50/50 duty cycle output. The modularity offers custom dividers to be quickly developed while maintaining minimum power usage. A multimodulus divider (MMD) receives an input signal and outputs an MMD output signal. The MMD includes a chain of modulus divider stages in such a way as to generate any divide value from 1 to 2(n+1)?1 (n is the number of cascaded elements) while maintaining a 50/50 duty cycle output. Power can be dramatically reduced as the frequency of each subsequent element is halved. The modular nature allows rapid development of any dividers simply by adding more elements to the chain.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventor: Alan J. Martin

Publication number: 20140003570Abstract: A frequency divider is disclosed. The frequency divider includes a multimodulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N?1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multimodulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.Type: ApplicationFiled: April 29, 2013Publication date: January 2, 2014Applicant: QUALCOMM IncorporatedInventor: Emmanouil Terrovitis

Patent number: 8598932Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd.Type: GrantFiled: May 6, 2013Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran

Patent number: 8599997Abstract: A multiplemodulus divider and an associated control method are provided. The multiplemodulus divider includes a divisor loader, a multiplemodulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiplemodulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a closeloop state or an openloop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the openloop state when the division period ends. The download signal corresponds to one of the modulus output signals.Type: GrantFiled: July 24, 2012Date of Patent: December 3, 2013Assignee: MStar Semiconductor, Inc.Inventors: YenTso Chen, JianYu Ding

Patent number: 8575914Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a highfrequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the highfrequency component reduced.Type: GrantFiled: May 20, 2010Date of Patent: November 5, 2013Assignee: Seiko Epson CorporationInventor: Masayoshi Todorokihara

Patent number: 8564336Abstract: A clock frequency divider circuit 11 according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by masking (SN) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency divider circuit 11 includes a mask control circuit that generates a mask signal in which a nonmask timing is preferentially assigned to a clock pulse at a timing at which no clock pulse exists in a clock signal used in a circuit Ai other than a target circuit Bi using the output clock signal among S clock pulses of the input clock signal, and a mask circuit that generates the output clock signal by masking a clock pulse of the input clock signal according to the mask signal generated by the mask control circuit.Type: GrantFiled: July 30, 2009Date of Patent: October 22, 2013Assignee: NEC CorporationInventor: Atsufumi Shibayama

Patent number: 8565368Abstract: A multimodulus divider includes a chain of n dual modulus divider cells in cascade and connected in a ripple configuration where the last (nk) of the divider cells are stateparked dual modulus divider cells. The stateparked dual modulus divider cells are forced to a given logical state when the divider cell is bypassed. The stateparked dual modulus divider cells ensure that the multimodulus divider can change between different number of cells without clock glitches or clock errors. The multimodulus divider is therefore capable of achieving a wide division range with seamless transition between division ratios.Type: GrantFiled: May 25, 2012Date of Patent: October 22, 2013Assignee: Micrel, Inc.Inventors: JuinnYan Chen, SanChieh Chou

Patent number: 8558589Abstract: The present disclosure provides circuitry and a method for digital clock generation including the generation of integer and noninteger sub clocks. The proposed method provides simplified constant signal propagation and low skew in the divided clock path independent of division factor. Also provided is a simplified mechanism for generating low power clock patterns divided down by factors which are noninteger, phaseshifted, repeated pulse trains, dynamically changing and glitchfree.Type: GrantFiled: February 22, 2012Date of Patent: October 15, 2013Assignee: Dialog Semiconductor GmbHInventors: Nir Dahan, Kevin Graham Allen

Patent number: 8559587Abstract: FractionalN divider circuits include a multimodulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multimodulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multimodulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.Type: GrantFiled: March 21, 2012Date of Patent: October 15, 2013Assignee: Integrated Device Technology, incInventors: Brian Buell, Benedykt Mika, ChenWei Huang

Patent number: 8558575Abstract: A system is provided for generating an output clock used for N.5 modulus division. An edgeslip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edgeslip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusiveor (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.Type: GrantFiled: March 23, 2012Date of Patent: October 15, 2013Assignee: APPLIED Micro Circuits CorporationInventor: Brian Abernethy

Publication number: 20130243148Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Inventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran

Patent number: 8532247Abstract: A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio.Type: GrantFiled: September 28, 2011Date of Patent: September 10, 2013Assignee: Texas Instruments IncorporatedInventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran

Patent number: 8521792Abstract: The present invention discloses a rate multiplication method for counting a sequence of original pulse signals and outputting a target pulse signal. In this method a comparison data and original pulse signal sequence is received. The original pulse signal sequence is counted in order to obtain a pulse count. Comparing the pulse count and the comparison data. If the pulse count is equal to the comparison data, a corresponding original pulse signal is outputted as the target pulse signal. Reset and recount the pulse count, and obtain which repeatedly. In this present invention the pulse count and the pulse interval between the target pulse signals can be determined freely according to a rate.Type: GrantFiled: February 16, 2009Date of Patent: August 27, 2013Assignee: VIA Technologies, Inc.Inventor: ChuanWei Liu

Patent number: 8508213Abstract: A frequency measurement device for measuring a frequency of a signal to be measured including a pulse signal, includes: a signal multiplier section that multiplies the signal to be measured by n (n is an integer) and outputs a multiplied signal; a counter section that counts the multiplied signal with a predetermined gate time and outputs a count value of the frequency of the signal to be measured at a predetermined period; and a lowpass filter that outputs a signal corresponding to the frequency of the signal to be measured based on the count value outputted at the predetermined period.Type: GrantFiled: May 18, 2010Date of Patent: August 13, 2013Assignee: Seiko Epson CorporationInventor: Masayoshi Todorokihara

Patent number: 8493105Abstract: An injectionlocked frequency divider (ILFD) including a signal injector, an oscillator (OSC), and a buffer stage is provided. The signal injector is configured for receiving an injection signal. The OSC is configured for dividing the frequency of the injection signal, so as to generate a first divided frequency signal, where there is an integralmultiple relation between the frequency of the first divided frequency signal and that of the injection signal. The buffer stage is configured for receiving and boosting the first divided frequency signal, and performing a pushpush process on the first divided frequency signal, so as to output a second divided frequency signal, where there is a fractionalmultiple relation between the frequency of the second divided frequency signal and that of the injection signal.Type: GrantFiled: December 28, 2011Date of Patent: July 23, 2013Assignee: Industrial Technology Research InstituteInventors: HongYeh Chang, YenLiang Yeh, ChiaHung Chang, ChunJen Chen

Patent number: 8461821Abstract: A frequency measuring apparatus includes: a highorder digit calculation section adapted to measure an input signal and output a highorder digit value of a frequency value of the input signal; a loworder digit calculation section adapted to measure the input signal and output a loworder digit value of the frequency value of the input signal; and an adding section adapted to add the highorder digit value and the loworder digit value to each other to output the frequency value of the input signal.Type: GrantFiled: May 20, 2010Date of Patent: June 11, 2013Assignee: Seiko Epson CorporationInventor: Masayoshi Todorokihara

Patent number: 8456203Abstract: A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a rereset circuit to output the switching signal to the selector based on the error.Type: GrantFiled: September 1, 2011Date of Patent: June 4, 2013Assignee: Fujitsu LimitedInventor: Masafumi Kondou

Patent number: 8422619Abstract: To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S?N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal.Type: GrantFiled: July 30, 2009Date of Patent: April 16, 2013Assignee: NEC CorporationInventor: Atsufumi Shibayama

Patent number: 8406371Abstract: Programmable divider circuitry is disclosed that utilizes two cascaded divider cells to generate division ratios from 4 to 7 and utilizes an output signal from one of the divider cells to sample and synchronize the divider output signal. The operation of the programmable divider circuitry improves the consistency of duty cycles generated across the different division ratios. Further techniques are also applied to make more consistent the duty cycles depending upon the division ratio selected.Type: GrantFiled: January 4, 2012Date of Patent: March 26, 2013Assignee: Silicon Laboratories Inc.Inventors: Francesco Barale, Mustafa H. Koroglu, Wenhuan Yu

Patent number: 8391438Abstract: The present invention discloses a method and apparatus for clock frequency division, the method comprises: determining a current frequency division coefficient in real time according to input clock signals and output clock information; then, performing counting on the input clock signals according to an integer portion and a decimal portion of the frequency division coefficient and a decimal scale threshold of the decimal portion; and performing accumulation on the decimal portion according to the counting result; finally, controlling the output clock according to the counting result and the accumulation result. With the method and the apparatus, output signals can be adjusted dynamically according to input signals, and the bit width of the integer portion and the decimal portion of the frequency division coefficient and the decimal scale threshold of the decimal portion can be increased on demand, so that the precision of the frequency division coefficient can be adjusted.Type: GrantFiled: September 17, 2010Date of Patent: March 5, 2013Assignee: ZTE CorporationInventor: Xuesong Wu

Patent number: 8369477Abstract: A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by a clock having a different frequency, and includes a mask control circuit 20 and a mask circuit 10. The mask control circuit 20 includes a mask timing signal generation circuit 22 that generates a mask timing signal 29 used to preferentially mask a clock pulse at a timing other than communication timings among M clock pulses of the input clock signal based on a communication timing signal 26, and a mask restraint circuit 62 that carries out a process to restrain masking of a clock pulse at a communication timing. The mask circuit 10 generates an output clock signal by masking clock pulses of an input clock signal according to a mask signal 50 generated by the mask control circuit.Type: GrantFiled: December 2, 2009Date of Patent: February 5, 2013Assignee: NEC CorporationInventor: Atsufumi Shibayama

Patent number: 8369476Abstract: A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a deltasigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the deltasigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.Type: GrantFiled: March 7, 2011Date of Patent: February 5, 2013Assignee: Industrial Technology Research InstituteInventors: WeiSheng Tseng, HongYi Huang, KuoHsing Cheng, YuanHua Chu

Publication number: 20130002319Abstract: A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.Type: ApplicationFiled: June 28, 2012Publication date: January 3, 2013Inventors: HwanSeok Yeo, JiHyun Kim

Publication number: 20120314833Abstract: A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio.Type: ApplicationFiled: September 28, 2011Publication date: December 13, 2012Inventors: Ramakrishnan Venkatasubramanian, Anthony Lell, Raguram Damodaran

Patent number: 8319532Abstract: A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.Type: GrantFiled: April 28, 2011Date of Patent: November 27, 2012Assignee: Mediatek Inc.Inventors: YuLi Hsueh, JingHong Conan Zhan